XX
TetraMem - Accelerate The World

ASIC/SoC Design Verification Engineer

  • +3
  • +9
  • US
    United States
Manifester de l'intérêt pour ce poste
  • +3
  • +9
  • US
    United States

À propos

1 month ago Be among the first 25 applicantsGet AI-powered advice on this job and more exclusive features.Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verificationBuild and maintain infrastructure/environment for automation verification of SoC architecture, function and performanceDevelop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levelsDevelop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-outWork with design engineers to debug and identify root causes of simulation failureSupport test engineers for post-silicon validationMentor and coach team members and junior engineers. Drive verification efficiencyResponsibilitiesCollaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verificationBuild and maintain infrastructure/environment for automation verification of SoC architecture, function and performanceDevelop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levelsDevelop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-outWork with design engineers to debug and identify root causes of simulation failureSupport test engineers for post-silicon validationMentor and coach team members and junior engineers. Drive verification efficiencyRequirementsMS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degreeIn depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodologyExtensive experience of building verification infrastructure, test planning, coverage closure, testbench and testcases development for function/performance verificationProficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly codingFamiliarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP coreExperience in verifying designs at both of RTL level and post-P&R gate levelAbility to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering teamExperience in one or more of the following areas considered a strong plus:Working knowledge of AI/ML Computing, GPU, ISP architectures and acceleratorsExperience in verifying mix-signal design and interface of digital and analogExperience of design verification for highspeed IO such as PCIE and DDRSalary Range: $110,000 - $300,000 / yearSeniority levelSeniority levelMid-Senior levelEmployment typeEmployment typeFull-timeJob functionJob functionStrategy/Planning and Information TechnologyIndustriesComputer Hardware ManufacturingReferrals increase your chances of interviewing at TetraMem - Accelerate The World by 2xSign in to set job alerts for “Design Verification Engineer” roles.Design Verification Engineer (University Grad)Sunnyvale, CA $114,000.00-$133,000.00 1 week agoSunnyvale, CA $114,000.00-$166,000.00 2 weeks agoMountain View, CA $132,000.00-$189,000.00 2 weeks agoSunnyvale, CA $114,000.00-$166,000.00 2 weeks agoASIC Design Verification I (Full Time) United StatesSan Jose, CA $92,500.00-$115,500.00 18 hours agoSan Jose, CA $149,600.00-$214,100.00 2 weeks agoSanta Clara, CA $138,452.00-$190,000.00 17 hours agoSOC Verification and Methodology EngineerSunnyvale, CA $114,000.00-$166,000.00 2 weeks agoSan Jose, CA $133,300.00-$186,800.00 8 hours agoPhysical Design and Verification EngineerSunnyvale, CA $142,000.00-$203,000.00 2 weeks agoMountain View, CA $107,900.00-$242,000.00 15 hours agoDesign Verification Engineer (Fulltime role only)Mountain View, CA $107,900.00-$242,000.00 3 days agoMountain View, CA $220,000.00-$270,000.00 2 weeks agoSunnyvale, CA $173,000.00-$249,000.00 2 weeks agoCPU Verification Engineer (Multiple Locations)San Jose, CA $133,300.00-$186,800.00 3 days agoWe’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI. #J-18808-Ljbffr

Compétences idéales

  • Verilog
  • Python
  • Perl
  • TCL
  • Shell Scripting
  • C
  • C++
  • ARM
  • PCIe
  • United States

Expérience professionnelle

  • Embedded
  • Hardware
  • Electronics Engineering

Compétences linguistiques

  • English