SoC Cache Design Engineer - RTL & Performance

Apple Inc.

United States

United States

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À propos

A leading technology company in Santa Clara is seeking a hardware engineer to design and develop cache subsystems for high-performance systems on chip (SoC). Responsibilities include tailoring hardware designs and ensuring optimal performance through architectural trade-offs. Candidates should possess a B.S. in a relevant field, with a knowledge of RTL design and memory subsystems. Benefits include a competitive salary, stock options, and comprehensive health coverage. #J-18808-Ljbffr

United States

Compétences linguistiques

English

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