About
Principal Analog Layout Engineer
- Minimum 5 years experience but ideally >8+ years experience
- Experience in 65nm and below (ideally 22nm and below)
- Understanding of layout for critical timing (PLL, DLL, clock distribution)
- Understanding of matching techniques xcfaprz for timing circuits and current cells
- Chip finishing experience a bonus
- Experience of Cadence PVS/QRC/Pegasus
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Languages
- English
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