Senior DDR IP Applications Engineer Presales LeaderCadence Design Systems • United States

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Senior DDR IP Applications Engineer Presales Leader

Cadence Design Systems

United States

United States

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About

A global electronic design automation company seeks a Senior Applications Engineer for DDR Design IP in San Jose, CA. This role involves supporting technical presales, conducting simulations, and presenting solutions to customers. Candidates should have a BS/MS in EE, knowledge of Verilog HDL, and excellent presentation skills. The annual salary range is $84,000 to $156,000, with competitive benefits and incentive compensation. #J-18808-Ljbffr

United States

Languages

English

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