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Senior ASIC Design Verification EngineerEthernovia • United States
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Senior ASIC Design Verification Engineer

Ethernovia
  • US
    United States
  • US
    United States
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Über

San Jose, CA About Ethernovia, Inc. Ethernovia is fundamentally changing how cars of the future are built by unifying in-vehicle networks into an end-to-end Ethernet system. Founded in 2018, we’re inventing the future of automobile’s communication! We are transforming automobiles’ communication network to enable the autonomous driving, electrical vehicle (EV) and software defined revolutions. Our breakthrough compute, communication, and software virtualization ushers in a new era of car connectivity and capabilities. We bring together, accelerate, and unify the car’s cameras/sensors, compute, and outside world to enable new advanced driver assistance features and services. With talented employees on 4 continents, we have filed > 50 patents to date. Join Ethernovia’s team to make a lasting impact on the future of mobility. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive their design from concept to silicon to their next car. Summary: As a Senior ASIC Verification Engineer, you will be
responsible for all aspects of digital SoC verification . You will work with architects, designers, and SW engineers to plan and execute verification and validation of
advanced automotive communication semiconductors and systems . You will contribute to a positive, trusting, and cohesive working environment based on integrity and strong work ethics. This position is located in:
San Jose, CA Key Qualifications: BS and/or MS in Electrical Engineering, Computer Science, or related field Minimum 10+ years of ASIC verification experience Strong understanding of ASIC verification fundamentals and industry standard methodologies Experience with
Verilog/System Verilog , UVM, Python, TCL, C/C++ Experience with the
full verification flow , from spec to coverage analysis to gate level simulation Debugging failures in simulation to root cause problems Self-motivated and able to work effectively both independently and in a team Additional Success Factors: Experience in any of the following areas: Networking
(Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols) Video standards, protocols, processing Digital signal processing filters Third party IP (SerDes, controllers, processors, etc.) Modular and Reusable Testbench architecture Design for re-use of pre and post silicon tests and infrastructure Automation of testbench creation, tests, regression, or EDA tools Knowledge of SystemC and/or DPI Personal Skills: Collaboration across multidisciplinary and international teams. What you’ll get in return: Technology depth and breadth expansion that can’t be found in a large company Opportunity to grow your career as the company grows Pre IPO stock options Cutting edge technology World class team Flexible hours Medical, dental and vision insurance for employees Flexible vacation time to promote a healthy work-life balance Salary Range: The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $180,000 - $230,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.
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  • United States

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  • English
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