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IP Logic Design EngineerIntel Corporation • Folsom, California, United States
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IP Logic Design Engineer

Intel Corporation
  • US
    Folsom, California, United States
  • US
    Folsom, California, United States
Jetzt Bewerben

Über

As an IP Logic Design Engineer, you will play a pivotal role in driving next‑generation semiconductor innovation. You will develop and optimize cutting‑edge IP logic designs, contributing directly to Intel’s mission to shape the future of computing. Your work will impact Intel’s success by delivering high‑quality IP blocks and subsystems for seamless integration into full‑chip designs, enabling superior power, performance, and efficiency in Intel’s products. Key Responsibilities
Develop logic design and register transfer level (RTL) coding for IP blocks using languages such as System Verilog and Verilog. Optimize logic designs to meet power, performance, area, and timing goals. Participate in defining architecture and microarchitecture features for IP blocks. Collaborate with cross‑functional teams to review verification plans, ensuring comprehensive validation of design features. Identify and resolve failures in RTL tests, implementing corrective measures to ensure design correctness. Apply power‑saving techniques such as clock gating and power gating to enhance energy efficiency. Support System‑on‑Chip (SoC) customers with the integration and verification of IP blocks, ensuring high‑quality handoff and smooth execution. Use industry‑standard tools and methodologies to ensure design integrity and compliance with quality assurance standards. Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or related field. 0 to 1 or more years of experience with a Bachelor's degree, or 0 years of experience with a Master's degree. Proficiency in RTL design and development using System Verilog and Verilog. Hands‑on experience with clock design, clock gating, and clock domain crossing. Experience with UPF low‑power coding and debugging techniques. Familiarity with problem‑solving approaches for power, performance, area, and timing optimization. Preferred Qualifications
Master's degree in Electrical Engineering, Computer Engineering, or related field. Understanding of microarchitecture design principles and strategies. Strong technical collaboration skills to work effectively in a team environment. Demonstrated ability to adapt to evolving technologies and industry trends. Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Work Model
This role will be eligible for a hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Equal Employment Opportunity
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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  • Folsom, California, United States

Sprachkenntnisse

  • English
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