Senior VLSI Physical Design EngineerXcelerium • Irvine, California, United States
Senior VLSI Physical Design Engineer
Xcelerium
- Irvine, California, United States
- Irvine, California, United States
À propos
We are seeking a highly skilled
Senior SoC/ASIC Physical Design Engineer
to lead and drive the physical design activities to successful closure by collaborating closely with RTL and other cross-functional engineering teams. You will be responsible for developing, refining and implementing cutting-edge flows and methodologies that optimize design performance, power efficiency, and area (PPA). Your expertise will directly contribute to achieving world-class time-to-closure and tapeout with optimal team size and resources. Responsibilities
Develop and Implement PD Flow:
Establish a modern physical design (PD) flow utilizing the latest EDA tool fusion and machine learning (ML) techniques to maximize PPA efficiency, optimize resource allocation, and achieve industry-leading time-to-closure and tapeout. End-to-End Physical Design Execution:
Perform partition synthesis and physical implementation, including synthesis, floorplanning, power/ground grid generation, place & route, timing, noise, physical verification, electromigration, voltage drop, and signoff checks. Methodology and Automation:
Create and refine physical design methodologies and automation scripts to streamline implementation and signoff processes. Cross-Functional Collaboration:
Work closely with RTL, DFT, and ASIC design teams to define architectural feasibility, establish timing, power, and area targets, and explore design trade-offs. Drive Design Closure:
Utilize an objective, metrics-driven approach to resolve design, timing, and flow issues and ensure predictability in achieving project milestones. Signoff Ownership:
Lead signoff closure activities, including static timing analysis (STA), noise analysis, logic equivalency, physical verification, and power integrity (EM/IR). Basic Qualifications
Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science (Master’s preferred). Experience:
10+ years of experience in ASIC/SoC physical design and flow development. Technical Proficiency:
Expertise in RTL-to-GDSII physical design and signoff flows. Strong experience with Synopsys EDA tools, understanding tool capabilities and underlying algorithms. Proficient in physical design methodologies: synthesis, place & route, STA, formal verification, CDC, and power analysis. Knowledge of FinFET and deep sub-micron CMOS technologies, including power dissipation, leakage, and dynamic behavior. Familiarity with DFT, Scan, MBIST, and LBIST methodologies and their impact on physical design.
Scripting and Automation:
Proficient in scripting languages (Python, Tcl, Perl, bash/csh) and automation using Makefiles. Analytical Skills:
Skilled in extraction and analysis of design parameters, QOR metrics, and implementing voltage scaling (SVS, DVFS) and SRAM split rail architectures. Team Collaboration:
Proven ability to work collaboratively in dynamic environments, lead design closure activities, and drive execution with a proactive, solution-oriented mindset. We provide competitive compensation package
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Compétences linguistiques
- English
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