Design Verification EngineerIntel Corporation • Santa Clara, California, United States

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Design Verification Engineer

Intel Corporation

Santa Clara, California, United States

Santa Clara, California, United States

Postuler Maintenant

À propos

Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to verification of next‑generation interconnect and chassis IPs that scale across multiple product families. You will work closely with senior engineers to build and execute robust verification plans, develop high‑quality reusable environments, and help deliver first‑pass silicon success through strong design verification practices. This role requires strong programming and algorithmic problem‑solving skills, hands‑on verification development, and willingness to work across traditional discipline boundaries. AI‑assisted workflows are part of everyday development here. Responsibilities
Develop and execute verification plans and testbenches for interconnect and chassis IP/features at IP and subsystem level. Build reusable verification components, checkers, constrained‑random tests, and debug infrastructure to improve coverage and productivity. Work with architecture, design, and software teams on spec reviews, feature clarification, bug triage, and closure; contribute outside strict DV boundaries when needed. Analyze simulation failures, root‑cause issues quickly, and drive fixes to closure with clear technical communication. Contribute to functional coverage planning, coverage closure, and quality sign‑off under guidance of technical leads. Contribute to both simulation and formal verification efforts; continuously improve verification automation, regression quality, and development efficiency. Minimum Qualifications
BS/MS in Electrical Engineering, Computer Science, or related field, with 3+ years of relevant experience in design verification. Programming fundamentals and algorithmic problem‑solving skills, with demonstrated hands‑on coding experience in SystemVerilog, C/C++, and Python. Foundation in simulation‑based verification methodologies UVM/ABV, with exposure to formal verification concepts; testbench development, debugging, and coverage‑driven verification. Hands‑on experience using AI‑assisted development tools as part of daily workflow for coding, debugging, and test development. Preferred Qualifications
Exposure to interconnects and bus protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, UCIe. Understanding of cache coherency and memory consistency models. Experience with external interfaces and system integration debug. Experience with formal verification tools (JasperGold, VC Formal, or similar) and emulation or FPGA‑based verification. Exposure to RTL concepts, physical design, or CAD tool flows. Prior work with system IPs such as MMUs, SMMUs, or IOMMUs and interrupt controllers. Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Annual Salary Range (US)
$141,910.00–200,340.00 USD Work Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site.
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Santa Clara, California, United States

Compétences linguistiques

English

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