Front-End Design Engineer
Qualcomm
- San Diego, California, United States
- San Diego, California, United States
À propos
Qualcomm Technologies, Inc. Job Area
Engineering Group, Engineering Group > ASICS Engineering General Summary
In this position, you will be responsible for RTL design and verification of digital IPs used across the board in Qualcomm chips. You will have the opportunity to work on critical high-speed clock IPs, power‑sequencing blocks integral to Qualcomm’s low power designs, custom FIFOs and high-speed latch arrays. The position also involves close collaboration with SOC design and verification teams on specification, integration, development, and support of front‑end deliverables for these Soft/Hard‑Macros. Minimum Qualifications
Bachelor’s degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Master’s degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. Ph.D. in Science, Engineering, or related field. Qualifications
Master’s degree in science, engineering or related field. 2+ years of professional or academic experience with RTL design or verification of digital IPs. Design verification knowledge and experience with design testbench suites. Good understanding of OOP concepts; experience in HVL such as System Verilog, UVM/OVM & System C. Familiarity with Power‑aware Verification is a plus. Good working knowledge of synthesis and STA. Knowledge of low power design techniques. Ability to work with transistor‑level circuit designers. Familiarity with ASIC backend integration tools for PNR (place & route) is a plus. Familiarity with IP delivery collaterals including behavior model, upf libs, LEF view, etc is a plus. Automation knowledge (Python) etc. will be a significant plus. Required for this Role
Education: Bachelors – Electrical Engineering; Bachelors – Science. Work Experience: 2+ years ASIC design, verification, or related work experience. Ability to use simulation and formal verification methodologies to execute test plans, write checkers, assertions and develop stimulus. Strong knowledge in digital logic design (data path and finite state machine (FSM) design). Skills: Verilog, System Verilog, Perl, circuit design. Pay Range and Other Compensation & Benefits
$115,600.00 - $173,400.00. This range reflects the broad minimum to maximum pay scale for this job code based on location. Additional compensation includes a competitive annual discretionary bonus program and opportunities for annual RSU grants. Qualcomm also offers a comprehensive benefits package that supports employees at work, at home, and at play. EEO Statement
Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.
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Compétences linguistiques
- English
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