Senior IC Design Verification Application EngineerCadence Design Systems • San Jose, Arizona, United States
Senior IC Design Verification Application Engineer
Cadence Design Systems
- San Jose, Arizona, United States
- San Jose, Arizona, United States
À propos
As an integral member of the North America Verification Field Applications Engineering (AE) Team, you will work directly with semiconductor and system companies to deploy Cadence’s verification platforms, including AI and ML technologies. This customer‑facing role provides front‑line technical support in the pre‑ and post‑sales process, working with the account team to develop solutions to customers’ verification challenges. Key Responsibilities
Establish technical credibility and rapport with customers, becoming the go‑to expert for technical inquiries and support. Collaborate with R&D to provide in‑depth technical assistance, supporting advanced verification flows and AI/ML applications. Champion customer needs and work closely with R&D and marketing to develop competitive, creative technical solutions. Understand the competitive landscape and continuously differentiate Cadence solutions. Write technical product literature such as application notes and technical articles. Review new product proposals and device specifications. Assume technical leadership roles in small teams as needed. Requirements
Minimum 7+ years of experience with SystemVerilog, VHDL, Verilog and verification skills such as UVM testbench architecture, development, and debugging. Strong RTL and testbench debugging skills. Experience scripting in Perl, Python, or Tcl. Strong software, HDL design and verification experience. Ability to quickly analyze verification environments and design complexity. Strong verbal and written communication skills. Strong teamwork skills. Ability to interact effectively with customers and R&D teams. Preferred Qualifications
Experience with C/C++/SystemC. Experience deploying VIPs in testbenches. Knowledge of protocols such as JTAG, UART, PCIe, AMBA, DDR. Knowledge of design fundamentals: architecture, micro‑architecture, HDLs, synthesis, timing. Digital design experience. Compensation
The annual salary range for California is $84,000 to $156,000. You may also be eligible to receive incentive compensation: bonus, equity and benefits. Sales positions generally offer a competitive OTE incentive compensation structure. Benefits
Paid vacation and paid holidays. 401(k) plan with employer match. Employee stock purchase plan. Medical, dental and vision plan options. Additional benefits may apply. Equal Employment Opportunity
Cadence is committed to equal employment opportunity throughout all levels of the organization. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability or any other protected class. Additional Information
Cadence participates in the E‑Verify program in certain U.S. locations as required by law.
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Compétences linguistiques
- English
Avis aux utilisateurs
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