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Senior ASIC Floorplan Design EngineerNVIDIA CorporationSanta Clara, California, United States
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Senior ASIC Floorplan Design Engineer

NVIDIA Corporation
  • US
    Santa Clara, California, United States
  • US
    Santa Clara, California, United States

À propos

Overview
NVIDIA is seeking an experienced ASIC Floorplan Engineer to design and implement the world’s leading SOCs, CPUs and GPUs. This role enables you to help shape the next generation GPU and SoC from early architecture development through physical design, impacting product lines ranging from consumer graphics to self‑driving cars and artificial intelligence. Responsibilities
Partner closely with product managers, chip architects, ASIC and physical design teams, and packaging teams to craft an optimal chip floorplan that balances cost/area, performance and power for the target market. Drive floorplan development and collaborate with ASIC and Physical design teams to identify and solve area, interconnect, timing and floorplan improvement opportunities to achieve optimal product features and cost. Develop AI workflows and productivity tools to continually improve existing infrastructure for optimizing chip area and speed of execution. Identify key technical and product risks and work with engineering and management teams to close on risk mitigation strategies. Qualifications
MSEE/MSCE (or equivalent experience) with broad and deep experience in chip development. 10+ years of experience developing SOC, CPU, graphics, memory and I/O sub‑systems. Ability to multi‑task across simultaneous projects and resolve complex technical issues among multi‑disciplinary engineering teams. Experience with physical design methodologies (flow and tools development), chip floorplan, power/clock/reset distribution, DFT, place and route, timing closure and packaging. Strong written, verbal and technical communication skills to present progress and options to align many teams. Experience with agentic AI workflows, Python, Perl and/or C++ programming. Ways to Stand Out
Experience driving development of large‑scale ASIC floorplans for chiplet‑based SOC or CPU projects. Strong algorithm development and programming skills. Ability to operate optimally in environments with incomplete data, evolving requirements and tight schedules. Benefits
Your base salary will be determined based on location, experience and the pay of employees in similar positions. The base salary range is $196,000 – $310,500 (USD). You will also be eligible for equity and additional benefits. Applications for this job will be accepted at least until June 25, 2026. Legal Statements
NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and is proud to be an equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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  • Santa Clara, California, United States

Compétences linguistiques

  • English
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