SoC Logic Design EngineerIntel • Santa Clara, California, United States
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SoC Logic Design Engineer
Intel
- Santa Clara, California, United States
- Santa Clara, California, United States
À propos
Key Responsibilities
Develop high‑quality logic designs, including Register Transfer Level (RTL) coding and simulations, for innovative SoCs.
Collaborate with architects to define and implement microarchitecture features of SoC blocks.
Integrate and validate Intellectual Property (IP) blocks and subsystems into full‑chip SoC designs.
Perform quality checks and optimize designs to meet power, performance, area, and timing objectives, ensuring seamless production readiness.
Review verification plans, confirm design features are thoroughly verified, and address any RTL test failures with corrective measures.
Employ secure development practices to mitigate security risks and maintain design integrity.
Work with IP providers to integrate and validate IPs at the SoC level.
Drive quality assurance compliance to enable efficient IP‑SoC handoffs.
Qualifications Minimum Qualifications
Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field and 4+ years of relevant experience.
OR Master’s degree in Electrical Engineering, Computer Engineering, or a related field and 3+ years of relevant experience.
OR PhD in Electrical Engineering, Computer Engineering, or a related field and 6+ months of experience.
Experience Must Be In
Expertise in RTL development, System Verilog, and SoC logic integration.
Proficiency in microarchitecture definition, logic design, and simulation.
Strong understanding of SoC design methodologies, including timing/power convergence and physical implementation.
Preferred Qualifications
Hands‑on experience with Python, Perl, or other scripting languages.
Familiarity with advanced Front‑End RTL Design tools such as Lint, CDC, Synthesis, and Static Timing Analysis (STA).
Experience in validation development, pre‑silicon testing, and DFT/DFD tools.
Knowledge of industry‑standard IPs, fabrics, and UVM‑based verification.
Job Type Experienced Hire
Shift Shift 1 (United States of America)
Primary Location US, Oregon, Hillsboro
Additional Locations US, California, Santa Clara; US, Texas, Austin
Business Group The Central Engineering Group (CEG) is Intel's data‑driven organization that builds scalable engineering solutions across three pillars: Product Enablement, Custom ASIC, and Foundry Enablement.
Position of Trust N/A
Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry, including competitive pay, stock bonuses, and comprehensive benefits such as health, retirement, and vacation.
Annual Salary Range $141,910.00 – $200,340.00 USD (US locations only)
Work Model for this Role This role will be eligible for a hybrid work model, allowing employees to split their time between working on‑site at their assigned Intel site and off‑site.
Additional Information Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates who are asked to pay any fees should report this immediately to their recruiter.
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Compétences linguistiques
- English
Avis aux utilisateurs
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