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Principal DRAM Design Engineer1000 Micron Technology, Inc. • Boise, Idaho, United States
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Principal DRAM Design Engineer

1000 Micron Technology, Inc.
  • US
    Boise, Idaho, United States
  • US
    Boise, Idaho, United States
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À propos

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We’re building the next generation of DRAM technology and pushing what’s possible at the intersection of device physics and circuit design. Our team thrives on solving deep technical challenges and turning innovative ideas into high‑performance, manufacturable memory solutions. If you’re excited about influencing future technology nodes and working on designs that ship at scale, you’ll feel right at home with us! As a Principal DRAM Design Engineer, you’ll play a critical role in shaping memory architectures and circuit innovations that directly impact product performance, power, and reliability. This is a hands‑on design role where your expertise will drive key decisions from concept through silicon validation, while collaborating with cross‑functional teams to deliver meaningful results. Responsibilities
Lead design and optimization of DRAM circuits including memory array, control logic, datapath, and test logic. Perform and analyze circuit simulations using tools such as SPICE and Verilog. Evaluate architectural trade‑offs impacting power, performance, and die size. Integrate layout parasitics into simulations and drive design for manufacturability. Define validation strategies including test chip development and silicon bring‑up. Minimum Qualifications
Bachelor’s degree in Electrical Engineering or related field. 2+ years of circuit design experience or 4+ years of product engineering experience. Strong understanding of analog and digital circuit fundamentals and debugging. Experience with circuit simulation tools and methodologies. Knowledge of CMOS behavior, timing, and performance optimization. Preferred Qualifications
Experience with memory architectures, especially DRAM array design and sense amplifiers. Familiarity with DFT/DFM concepts and semiconductor test flows. Experience working with layout parasitics and advanced process nodes. Ability to communicate complex technical concepts clearly across teams. Interest or experience in applying AI tools to engineering workflows. Benefits
Choice of medical, dental and vision plans across all locations. Benefit programs that protect income if unable to work due to illness or injury. Paid family leave, robust paid time‑off program and paid holidays. Additional benefits available through Micron Benefits Guide. Equal Opportunity
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
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  • Boise, Idaho, United States

Compétences linguistiques

  • English
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