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À propos
Develop die-to-die chiplet PHY IP, including PLLs and key analog/mixed-signal blocks Manage the full lifecycle of design, verification, layout interaction, tape-out, and silicon bring-up to ensure production quality Collaborate with architecture, analog, digital, verification, layout, and software teams to integrate and optimize AMS IP
Required qualifications
10+ years of analog/mixed-signal IC design experience in FinFET, including PLL/AMS design, with an MSEE/PhD or equivalent background Strong track record in production tape-outs and silicon bring-up/testing, with hands-on use of industry-standard EDA tools Deep experience in high-speed datacomm/SerDes and die-to-die PHY design, including Tx/Rx, DDR, PCIe, and USB PHY components Expertise across key circuits such as bias generators, amplifiers, LDOs, ADCs/DACs, and oscillators Familiarity with high-speed digital and equalization techniques like CTLE, DFE, and de-emphasis
Compétences linguistiques
- English
Avis aux utilisateurs
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