Debug/Trace/Profiling Design EngineerSiFive • Santa Clara, California, United States

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Debug/Trace/Profiling Design Engineer

SiFive

Santa Clara, California, United States

Santa Clara, California, United States

À propos

Job Description Hardware Design Engineer – responsible for designing and enhancing debug, trace, and profiling IP for SiFive’s RISC‑V processor subsystem. This role focuses on architecting, designing, and implementing debug, trace, and profiling hardware, integrating it into SiFive’s Chisel/FIRRTL framework, and ensuring high‑quality documentation and collaboration. It requires working closely with architecture, performance, software, and hardware teams and engaging with customers, partners, tools vendors, and the RISC‑V International Association. Responsibilities Architect, design, and implement debug, trace, and profiling hardware. Collaborate with architecture, performance, software, and hardware teams on microarchitecture exploration and specification. Implement RTL generators enabling extensive configurability as a first‑class consideration. Integrate new design content into SiFive’s Chisel/FIRRTL framework, contributing to framework improvements for automatic configuration, documentation, verification testbenches, and packaged software. Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans. Document and share knowledge through clear documentation and active participation in a collaborative design culture. Requirements Knowledgeable in debug, trace, and profiling architecture and concepts. Knowledgeable in debug interfaces, JTAG, and cJTAG. Knowledgeable in CPU architectures, power management, and SoC design. Experience in debugging tools and profiling methods. Proficiency with hardware (RTL) design in Verilog, SystemVerilog, or VHDL. Attention to detail and focus on high‑quality design. Ability to work well with others and belief that engineering is a team sport. Knowledge of at least one object‑oriented and/or functional programming language. Familiarity with Chisel/Scala, RISC‑V architecture, Git/Jira/Confluence is a plus. 7+ years of industry experience leading and directly contributing to architecture, microarchitecture, and RTL design for debug/trace/profiling hardware for high‑performance processors. MS/PhD in EE, CE, CS, or a related technical discipline. Pay & Benefits Base Pay Range: $158,760.00 – $194,040.00. In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity. Candidates are also eligible for a comprehensive, competitive benefits package, which may include healthcare, retirement plans, paid time off, and more. Additional Information This position requires successful background and reference checks and satisfactory proof of your right to work in the United States of America. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export‑controlled technology under applicable export control laws, or that we can obtain necessary export licenses or approvals. Equal Opportunity Employer SiFive is an equal‑opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E‑Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I‑9, Employment Eligibility Verification, upon hire. We do not use E‑Verify to pre‑screen job candidates and will comply with all E‑Verify regulations.
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Santa Clara, California, United States

Compétences linguistiques

English

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