Physical Design Engineer

Sintegra

United States

United States

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À propos

Job Description We are seeking expert Physical Design Engineers to lead top-level signoff activities for complex SoCs on advanced nodes (5nm / 3nm / 2nm). The ideal candidate will have multiple full-cycle tapeouts and the technical depth to independently drive signoff-to-tapeout closure. This role requires close collaboration with RTL, Timing, Power Integrity, and Foundry teams to ensure structural integrity, timing convergence, and power reliability for high-performance silicon. Core Responsibilities Drive top-level signoff for high-performance SoC designs. Collaborate with RTL, Physical Design, STA, and cross-functional teams. Execute, analyze, and debug complex full-chip design challenges. Develop and optimize signoff methodologies to improve TAT (Turn-Around Time) and PPA (Power, Performance, Area). Identify and mitigate timing, power, reliability, and clocking risks at full-chip level. Deliver signoff closure and tapeout readiness independently. Specialized Tracks (Expertise in at least one area) Track 1: Top-Level EMIR (Power Integrity) Perform Static & Dynamic IR Drop analysis. Execute Electromigration (EM) verification. Optimize PDN for reliability and noise margins. Tools: Ansys RedHawk-SC, Cadence Voltus. Track 2: Top-Level Timing & STA Own full-chip STA across all PVT corners and modes. Manage MMMC timing closure and ECOs. Tools: Synopsys PrimeTime, Cadence Tempus. Track 3: Top-Level Clock Distribution Design and analyze clock architectures (H-Tree, Mesh, Hybrid). Drive CTS for ultra-low skew and balanced latency. Tools: Cadence Innovus, Synopsys Fusion, SPICE simulation. Required Qualifications BS/MS in Electrical/Computer Engineering or related field. 8+ years of experience in Physical Design/Signoff. Proven track record with 2–3 successful tapeouts on advanced nodes (5nm, 3nm, 2nm). Deep knowledge of OCV, AOCV/POCV, statistical timing methodologies. Strong scripting skills (Tcl, Python, Perl). Excellent debugging, analytical, and communication skills. Preferred Skills Experience with 2.5D/3D IC packaging signoff. Familiarity with foundry signoff methodologies (TSMC, Samsung, Intel). Background in HPC, AI accelerators, or large-scale SoC designs.

United States

Compétences linguistiques

English

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