Job Opportunities

Senior Applications Engineer DDR Design IPAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The Cadence IP team develops industry leading IP

Lead Applications Engineer – DDR Design IP page is loaded## Lead Applications Engineer – DDR Design IPlocations:SAN JOSEtime type:Full timeposted on:Posted Yesterdayjob requisition id:R51279## **At Ca

**Job Title:****Principal Design Engineer****(Memory)** **Location:****Cork** The Principal Design Engineer will be based in Cork, as part of an experienced Controller IP Team with long established Co

Senior IC Design Verification Application Engineer page is loaded## Senior IC Design Verification Application Engineerlocations:SAN JOSEtime type:Full timeposted on:Posted Todayjob requisition id:R519

Altera.Senior FPGA System Level Applications Engineer page is loaded## Senior FPGA System Level Applications Engineerlocations:San Jose, California, United Statestime type:Full timeposted on:Posted Ye

Cupertino, California, United States HardwareDo you love crafting elegant solutions to highly sophisticated challenges? As part of our Silicon Technologies group, you’ll help design and manufacture ou

401(k) 401(k) matching Relocation bonusSr Design Verification Engineer Milpitas, CAPrimary ResponsibilitiesResponsible for all aspects of verification methodology employed and for ensuring the applica

## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Te

Cadence Job OpportunityAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Specific duties include: Be responsible for high-performance memory

Staff Logic Design Engineer page is loaded## Staff Logic Design Engineerlocations:US - Milpitas, CAtime type:Full timeposted on:Posted 3 Days Agojob requisition id:REQ31773**Be visionary**Teledyne Tec

Application Engineering Architect page is loaded## Application Engineering Architectlocations:SAN JOSEtime type:Full timeposted on:Posted Todayjob requisition id:R51716## **At Cadence, we hire and dev

Avicenais a privately held company developing microLED-based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and

Sr Principal Design Engineer page is loaded## Sr Principal Design Engineerlocations:SAN JOSEtime type:Full timeposted on:Posted Todayjob requisition id:R52250## **At Cadence, we hire and develop leade

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technolog

Job Family:SoftwareReq ID:468611Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative el

Company: Qualcomm Technologies, Inc.Job Area: Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:Familiarity with RTL design in Verilog and System VerilogDevelop verification meth

Senior Engineer, Field Applications page is loaded## Senior Engineer, Field Applicationslocations:US, CA, San Jose, Rio Roblestime type:Full timeposted on:Posted Yesterdayjob requisition id:R258790**A

Senior Engineer, Product Applications page is loaded## Senior Engineer, Product Applicationslocations:US, CA, San Jose, Rio Roblestime type:Full timeposted on:Posted Todayjob requisition id:R257895**A

Applications Engineer/Sr. Applications Engineer page is loaded## Applications Engineer/Sr. Applications Engineerremote type:Onsitelocations:Kirkland, WA:San Jose - Californiatime type:Full timeposted

Avnet Field Applications EngineerAt Avnet, relationships matter. We are a global, FORTUNE 500 technology distributor and solutions company that delivers design, supply chain and logistics expertise to

Avicenais a privately held company developing microLEDbased ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and

Senior Engineer I- Applications page is loaded## Senior Engineer I- Applicationslocations:CA - Roseville:CA - San Jose - 3870 N. First Sttime type:Full timeposted on:Posted Todayjob requisition id:R24

Senior Level Application/System Engineering PositionMonolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in In

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Applicants selected will be subject to a government security investigation and

We’re hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the designs that will bring our next-generation AI processors to life. About