About
Design Verification Engineer Location:
Minneapolis, MN Duration:
12 Months
Open to relocation candidates across USA who can relocate on their own expense.
Job Summary: Seeking an experienced Design Verification Engineer to own end-to-end pre-silicon functional verification for a high-speed mixed-signal PHY test chip from DV planning through coverage closure and tape-out signoff. Responsibilities include UVM/SystemVerilog testbench development, regression management, assertions, formal verification, debugging, and post-silicon support.
Required Skills:
6–12 years of DV experience in UVM/SystemVerilog environments
Hands-on experience building UVM testbenches from scratch
Verification of I2C, SPI, APB, AHB, or similar interfaces
Functional/code coverage modeling and coverage closure
SystemVerilog Assertions (SVA) and regression/debugging skills
Experience with RTL debugging, waveform analysis, and tape-out support
Strong ownership mindset in small, high-accountability teams
Preferred:
Formal verification tools (JasperGold, VC Formal)
Mixed-signal or PHY verification experience
BS/MS/PhD in Electrical/Computer Engineering or related field
Languages
- English
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