About
Pursuing a
B.S., M.S or PhD
in Electrical Engineering, Computer Engineering, Computer Science, or a related field with a focus on
digital design and verification . Strong understanding of
digital logic design
and
computer architecture
(pipelines, caches, interconnects, memory systems). Familiar with
HDLs such as Verilog/SystemVerilog , and interested in learning
Formal verification, Cocotb, and UVM‑based verification methodologies . Comfortable working in
Linux‑based development environments
and using scripting languages (e.g.,
Python, Shell, Perl ) to automate tasks. Detail‑oriented problem solver who enjoys
debugging complex issues , reasoning about corner cases, and working from specifications. Collaborative team member with clear communication skills, able to document work and discuss trade‑offs with RTL, architecture, and validation teams. What We Need
Help
develop and maintain SystemVerilog/UVM testbenches
for SoC IP blocks and subsystems, including stimulus, checkers, and scoreboards. Write and refine
verification test plans
from architectural and micro‑architectural specifications, with a strong focus on corner cases and coverage. Develop
constrained‑random and directed tests , run regressions, and triage failures by working closely with RTL designers to root‑cause issues. Analyze
functional and code coverage results , identify gaps, and propose additional tests or checks to drive coverage closure. Contribute to
automation and infrastructure
(scripts, Makefiles, CI hooks, dashboards) that improve verification productivity and debug turnaround time. Partner with
cross‑functional teams
(architecture, design, performance, validation) to align on expected behavior and sign‑off criteria for silicon. Have impact measured through
coverage metrics achieved, quality and reproducibility of bugs found, and robustness of the verification environment you help build. What You Will Learn
Industry‑standard
verification methodologies (SystemVerilog/UVM) , including testbench architecture, stimulus generation, and scoreboard/checker design. Hands‑on experience with
simulation, regression, and coverage tools
used in large‑scale industrial verification environments. How to
read and interpret hardware specifications , micro‑architecture documents, and timing diagrams, and translate them into actionable tests and assertions. Exposure to
high‑performance interconnects, memory controllers, and accelerators , and how they are verified at IP, subsystem, and SoC levels. Best practices for
collaborating in a silicon development team , including code review, documentation, and cross‑site communication. USA Hiring Timelines
This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles: Fall Term: Sept–Dec work term, Jan–Aug recruit. Please note these timelines are for reference only. Actual timelines may vary. This offer of employment is contingent upon the applicant being eligible to access U.S. export‑controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded. As set forth in Tenstorrent University Jobs’s Equal Employment Opportunity policy, we do not discriminate on the basis of any protected group status under any applicable law. If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection. As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measure the effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categories is as follows: A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service‑connected disability. A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service. An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense. An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.
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Languages
- English
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