Senior ASIC Verification Engineer: Sensor Tech & UVM

We’re partnered with a global technology leader at the forefront of next-generation connectivity and intelligent systems. This team is driving innovation in sensor technologies that power smarter, more connected devices across a wide range of applications.

This is a great opportunity to join a highly collaborative engineering group working on complex ASIC developments, with strong flexibility and a modern hybrid working environment based in Cork.

The Role

You will play a key role in the verification of advanced sensor algorithms and ASIC designs, contributing across the full verification lifecycle in a fast-paced, technology-driven environment.

Responsibilities

• Develop and deploy industry-leading verification methodologies including UVM and formal verification
• Build and maintain reusable verification environments (UVCs, testbenches, C models)
• Verify RTL for sensor algorithms to tapeout quality
• Create detailed test plans in collaboration with design and systems teams
• Integrate C models within UVM frameworks
• Write SystemVerilog assertions and perform coverage-driven verification
• Debug and analyse test failures, ensuring bit-accurate validation against test vectors
• Analyse coverage and work closely with design teams to close gaps
• Support regression frameworks and debug regression failures
• Contribute to subsystem-level integration, including test planning and debug
• Develop Python automation to improve workflows and efficiency
• Participate in design and project reviews

What they're looking for:

• BSc in Engineering, Computer Science, or related field
• 8+ years’ experience in ASIC verification or UVM-based functional verification
• Strong expertise in SystemVerilog, UVM, and RTL simulation
• Experience with constrained-random and coverage-driven verification methodologies
• Strong debugging skills and experience achieving coverage closure
• Scripting experience with Python, Perl, or shell
• Familiarity with C/C++

Nice to have skills:

• Formal verification tools such as Jasper or VC Formal
• SystemC or MATLAB experience
• Gate-level simulation and power analysis exposure

What's in it for you?

• Flexible hybrid working with a mix of home and office
• State-of-the-art office in Cork
• Strong focus on work-life balance, including flexible remote working options
• Opportunity to work on cutting-edge sensor technologies
• Collaborative and innovation-driven engineering culture
• Excellent base, bonus and equity on offer

If you’re interested in working on complex ASIC verification challenges within a forward-thinking environment, feel free to apply or reach out directly for a confidential discussion. xcfaprz

If this sounds interesting and you'd like to learn more, click the link below to apply or email me with a copy of your CV on

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