Design Verification Engineer (Medior)

AsicPro is on the lookout for a Design Verification Engineer, Medior level (Remote: Ireland, Serbia, Greece) to join our growing engineering team. If you're passionate about building high-quality silicon and want hands‑on experience in ASIC/SoC verification, AsicPro offers challenging projects and the chance to expand your technical expertise across multiple verification flows.

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• You have solid foundational experience in ASIC/SoC verification
  
• You're prepared to learn and take ownership of verification tasks
  
• You enjoy collaborating with colleagues and contributing to a strong engineering culture
  
• You value modern verification methodologies and strive for high‑quality results
  

We don’t expect you to tick every box, but strong verification fundamentals, hands‑on experience and a willingness to learn are key.

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• B.Sc. or M.Sc. in Electrical Engineering, Computer Science, or a related field
  
• 4+ years experience in ASIC/SoC verification
  
• Fluent in English with excellent communication skills
  
• Strong problem‑solving abilities and attention to detail
  
• Proficiency with SystemVerilog, UVM and debugging methodologies
  
• Scripting skills (Perl, Python, TCL, Makefile)
  
• Experience with Specmen/e, assertions and formal verification methods
  
• Familiarity with hardware‑software co‑verification flows
  

If you already have extensive experience, you may want to explore our Senior Verification Engineer opening.

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• Impactful work: Contribute to high‑impact semiconductor projects with international clients
  
• Collaborative Culture: Supportive leadership and a learning‑focused environment
  
• Professional Growth: Opportunities to expand your skills and knowledge in verification methodologies
  
• Annual Meetups: In‑person team gatherings to connect, learn and build strong working relationships
  

To apply, please complete the form below and a member of our HR team will review to see if your skills and experience are a match for ongoing project requirements. xcfaprz

Alternatively, you can email your application directly to with the subject line: "Design Verification Engineer".