Staff Logic Design Engineer

We are looking for a top-notch Staff Logic Design engineer who has the right composition of knowledge, experience, team play, spirit and drive, to join a dynamic team that develops leading edge test and measurement products. Join our high-speed Protocol Team as a Staff Logic Design Engineer, where you'll architect and implement high-performance digital logic for protocol capture, analysis, and emulation. You'll work on FPGA-based systems that decode and analyze High speed protocols (PCIe, USB, Ethernet etc.) in real time, collaborating with cross-functional teams to deliver industry-leading solutions.

Key Responsibilitie

s

RTL Design & Microarchitectu

• reDevelop synthesizable RTL (Verilog/SystemVerilog) for high-speed protocol, packet parsing, timestamping, and buffer managemen
• t.Design high-throughput data paths and control logic optimized for latency, bandwidth, and resource efficienc

y.FPGA Developme

• ntTarget high-end FPGAs (Xilinx Versal, Intel Agilex); perform synthesis, P&R, timing closure, and resource optimizatio
• n.Integrate PCIe IP cores, DMA engines, and custom protocol decoder

s.Verification & Deb

• ugBuild SystemVerilog/UVM testbenches for block and system-level verificatio
• n.Conduct simulation, waveform analysis, and functional coverage to ensure robust desig

n.System Integrati

• onCollaborate with hardware, firmware, and software teams to bring up and validate protocol analyzer platform
• s.Support lab debug using logic analyzers, oscilloscopes, and in-system FPGA tools (ILA/SignalTap

).Documentation & Proce

• ssCreate design specifications, interface documents, and verification plan
• s.Participate in design/code reviews and contribute to continuous improvement of design practice

**s.

Required Qualificati**

• ons

BS in EE, CS or Computer Engineering requ
- iredMS in EE is a
- plus7+ years of experience in digital logic design for FPGA or
- ASICStrong proficiency in Verilog/SystemVerilog RTL de
- signExperience with one or more of the following protocols: PCIe, CXL, NVMe, USB, SAS,
- SATAExperience with Monitoring and/or Test & Measurement t
- oolsExperience with PCIe protocol (Gen4/Gen5/Gen6) and familiarity with TLP/DLLP/PHY layer conc
- eptsHands-on with FPGA toolchains (Vivado, Quartus, etc.) and timing clo
- sureKnowledge of UVM, assertions, and simulation/debug tools (e.g., ModelSim, Vivado Simula
- tor)Solid understanding of CDC, clock domain design, and reset strate

**gies

Preferred Qualifica**

• tionsExperience with protocol analyzers, packet capture, and timestamping
• logicFamiliarity with AXI interconnects, memory controllers, and high-speed buff
• eringExposure to SERDES, PCIe IP integration, and link training/
• debugScripting experience (Python, Tcl) for automation and test infrastru
• ctureExperience with hardware/software co-design, register maps, and embedded firmware intera
• ctionPrior work in test & measurement or semiconductor validation environ

**ments

Work Envir**

• onmentLocation: Milpit
• as, CATravel: Minimal (