Member of Technical Staff, ASIC Design Engineer

• Design and implement RTL for complex Mixed Signal ASIC SoCs.
• Develop and integrate ARM-based processor subsystems and SoC interconnect fabrics.
• Drive architecture, microarchitecture, and RTL development of digital logic blocks.
• Collaborate closely with analog/mixed-signal, verification, DFT, and physical design teams.
• Perform logic synthesis, DFT insertion, STA, and generate timing constraints.
• Run and resolve issues from LINT, CDC, and Formal Verification tools.
• Support post-silicon validation and bring-up activities as needed.

• BSEE or MSEE in Electrical Engineering or related field.
• 5+ years of hands-on experience in RTL design, preferably in Display Controllers, Touch Controllers, Wired/Wireless Communication Systems and Automotive Sensor Communication Systems.
• Strong experience in developing ARM-based processor subsystems and SoC fabrics.
• Strong expertise in Verilog and SystemVerilog.
• Solid understanding and practical experience with CDC (Clock Domain Crossing), LINT tools, Synthesis, Formal Verification, and Static Timing Analysis (STA).
• Experience with design for testability (DFT), scan insertion, and ATPG.
• Proficiency in scripting languages such as Python or Perl.
• Experience working at both block-level and full-chip integration.
• Experience in DSP (Digital Signal Processing) design.
• Knowledge of analog/mixed-signal interaction and integration.
• Familiarity with industry-standard EDA tools (Synopsys, Cadence, Siemens/Mentor).
• Experience in low-power design techniques.
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Nice-to-have skills

• Verilog
• SystemVerilog
• Python
• Perl
• Digital Signal Processing
• Cadence

• San Jose, California

Work experience

• Electronics Engineering

Languages

• English