About
At Apple, we work every day to craft products that enrich people's lives. If you're passionate about tackling unsolved challenges, we have an exciting opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you early in your journey towards a chip design career and wish to challenge yourself in a technical and multi-disciplinary endeavor? If so, this is an exciting position in the world class Apple mixed-signal silicon design team! This position will build on a solid foundation in digital logic circuits and provide an introduction into understanding analog circuits. You will work with a variety of flows fundamental to modern silicon engineering: model and integrate high mixed signal and analog IPs into high-speed digital circuits ensuring formal equivalence between custom designs and their abstract representation. This is a great chance to gain valuable experience and knowledge in software methods and analysis, which are increasingly crucial across various disciplines. As a member of our wide-ranging group, you will have the exceptional opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every day. You will be working to specify, design, and help in the verification and lab bring-up of sophisticated mixed-signal circuits (digital side). In this job you will be responsible for specifying and/or micro-architecting digital blocks in sophisticated mixed-signal circuits. You will be responsible for RTL coding of blocks specified by you or others. You will also participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will contribute to the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc. Minimum qualifications: BS degree in technical discipline with minimum 3years of proven experience. Preferred qualifications: Proven knowledge of RTL design, Verilog and SystemVerilog Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers) Strong communication and presentation skills Solid understanding of mixed signal concepts is a plus Validated knowledge of synthesis, static timing and DFT is a plus Validated knowledge of SystemVerilog assertions, checkers, and other design verification techniques are a plus Knowledge of scripting languages; Perl and Python are a plus At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $139,500 and $258,100, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses
including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Apple accepts applications to this posting on an ongoing basis.
Languages
- English
Notice for Users
This job comes from a TieTalent partner platform. Click "Apply Now" to submit your application directly on their site.