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- +4
- California, United States
About
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience in Physical Design.
Experience with synthesis/PnR tools (e.g., Genus, Innovus, Design Compiler, ICC).
Experience in high-performance synthesis, PnR, sign-off convergence, including STA and sign-off.
Preferred qualifications:
Experience with ASIC design flows and physical design methodology.
Experience in low power design implementation, including UPF/CPF, multi-voltage domains, power gating.
Proficiency in scripting languages such as Tcl or Perl.
Knowledge of computer architecture, Verilog or SystemVerilog.
Understanding of circuit design, device physics, and deep sub-micron technology.
Role overview:
Join a team that pushes boundaries by developing custom silicon solutions powering the future of Google's products. Contribute to innovations that impact millions worldwide, shaping next-generation hardware for performance, efficiency, and integration.
Salary range:
The US base salary range for this full-time position is $132,000 - $189,000 plus bonus, equity, and benefits. Salary ranges are role, level, and location-dependent. Specifics can be discussed with your recruiter during hiring.
Additional notes:
The listed compensation reflects base salary only; bonus, equity, and benefits are additional.
Learn more about benefits at
Google Benefits .
Responsibilities:
Define and implement innovative methodologies to improve performance, area, and power.
Develop ASIC RTL to GDS implementation for designs.
Manage physical implementation for partitions.
Collaborate with cross-functional teams to deliver results.
Google is an equal opportunity employer committed to diversity and inclusion. For accommodations, please complete our
Accommodations for Applicants form .
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Nice-to-have skills
- Perl
- SystemVerilog
- TCL
- Verilog
Work experience
- Embedded
- Hardware
- Electronics Engineering
Languages
- English
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