Senior IP Design Engineer
DCV Technologies
- Belfast, Northern Ireland, United Kingdom
- Belfast, Northern Ireland, United Kingdom
About
As a Senior IP Design Engineer you will design and implement SystemVerilog RTL, develop synthesis‑ready IP targeting FPGA / Adaptive SoC platforms, and own the end‑to‑end design flow including RTL architecture, integration, timing closure, place‑and‑route, constraints and optimisation. The role focuses on high‑speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows.
Key Responsibilities
Design high‑performance IP using SystemVerilog RTL for FPGA/Adaptive SoC
Deliver synthesis‑ready RTL meeting timing, P&R and integration requirements
Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks
Drive timing closure using Vivado toolchains
Develop automation using Python/Tcl scripting
Collaborate with hardware, SoC, firmware and integration teams
Essential Skills
Strong SystemVerilog RTL design experience
FPGA/Adaptive SoC design flow: synthesis, P&R, timing closure
High‑speed digital interfaces: 100GbE / PCIe Gen5 / AXI
Vivado / Vitis toolchain expertise
Python/Tcl, Git, CI/CD experience
Details
Contract: 6 months + extension
Location: Remote (UK)
Start: ASAP
Rate: Market rate
If you are a Senior IP Design Engineer with strong FPGA RTL, high‑speed interface IP and Xilinx toolchain experience, please apply with your CV for immediate consideration.
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Languages
- English
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