Senior PLL IC Design Engineer

Senior IC Design Engineer

Location: San Diego, CA (onsite/hybrid)

Eligibility: US Citizen or US Permanent Resident (preferred)

Employment Details: Full-Time + Health Benefits + 401K Plan + PTO + Founder Shares

Requirements:

Experience with high-speed time-interleaved ADCs (SAR, pipeline, TDC, etc.), RF front-end design, SerDes, and other data converters, filters, amplifiers, PLLs, power management, oscillators, etc., in FinFET technologies.

MS degree with 5+ years of relevant experience or PhD with 3+ years of relevant experience.

Strong experience with PLL and clock distribution is preferred.

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