Senior IP Design Engineer
DCV Technologies
- London, England, United Kingdom
- London, England, United Kingdom
About
Develop and implement SystemVerilog RTL for FPGA / Adaptive SoC designs Design and optimise high-speed connectivity IP (PCIe Gen5, 100Gb Ethernet, AXI/AMBA) Support synthesis, P&R, timing analysis and timing closure Collaborate with cross-functional teams on integration and validation Contribute to CI/CD workflows, scripting, and automation (Python, Tcl) Provide documentation, status updates and technical input Required Skills
Strong SystemVerilog RTL design background for FPGA / SoC Hands-on experience with AMD/Xilinx toolchain - Vivado, Vitis Expertise in PCIe, 100GbE, AXI/AMBA, and high-speed interface design Experience in synthesis, place & route, timing closure Scripting in Python and Tcl; experience with Git and CI pipelines Ideal Background
FPGA / SoC development (Versal, UltraScale, Zynq) High-speed networking, telecommunications or semiconductor engineering Strong RTL ownership from concept through timing-closed delivery Contract Details
6-month contract Remote across UK, Ireland, Eastern Europe Competitive daily rate If you are an experienced Senior RTL / IP / FPGA Design Engineer with strong SystemVerilog and high-speed protocol expertise, we'd like to hear from you. Apply now with your latest CV
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Languages
- English
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