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About
Position: Digital IC Design Engineer
Location: Paris – France
The company’s design team is seeking a dynamic and highly motivated Digital IC design engineer who will participate in the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market. The candidate will be particularly involved in the architecture definition, design, and verification of the ASIC digital sub-blocks in close collaboration with the mixed-signal and digital IC design engineers.
Responsibilities:
- Derive specifications and define the micro-architecture of the digital sub-blocks
- RTL design of the digital sub-blocks (Verilog/System-Verilog)
- Elaborate a detailed verification plan corresponding to the circuit specifications
- Write SDC constraints
- Define block and top-level self-checking test benches RTL and gate level netlist
- Participate in the evaluation of the fabricated ASIC in our measurement lab
- Work in a team to successfully design a state-of-the-art ASIC
- Participate in design reviews
- Write documentation in accordance with company QA policy
Qualifications and Requirements:
- You have a MSc or PhD in Electrical Engineering or equivalent and 3+ years of hands-on experience in micro-architecture definition, RTL design, and verification
- You have a solid background in digital electronics and signal processing
- You have solid knowledge of digital hardware description languages (VHDL or Verilog) and scripting languages (TCL, Perl, Python)
- You have solid knowledge of System Verilog
- Experience with UVM methodology is a plus
- You demonstrate good analytical and problem-solving skills
- A previous experience in design and verification of digital functions for Mixed-Signal ICs such as A/D Converters, D/A Converters, and/or RF transceivers is a plus
- A previous experience with Cadence or Synopsys RTL design flow is a plus
- You are a team player with a critical attitude and sense of initiative
- You communicate fluently in English (oral and written)
If you are interested in the role please contact: Jessica@microtech-global.com #J-18808-Ljbffr
Nice-to-have skills
- CMOS
- Verilog
- SystemVerilog
- VHDL
- TCL
- Perl
- Python
- Cadence
Work experience
- Embedded
- Hardware
- Electronics Engineering
Languages
- English