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LanceSoft, Inc.

Design Verification Engineer

  • +2
  • +5
  • US
    California, United States
  • +2
  • +5
  • US
    California, United States

About

This range is provided by LanceSoft, Inc. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range
$90.00/hr - $90.00/hr Recruitment Specialist at LanceSoft, Inc. Semiconductor / VLSI / EDA / Embedded
Pay Rate: $85/hr to $95/hr on W2 Remote Responsibilities
Ideally Masters + 5 years or Bachelors + 8 years is preferred Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Seniority level
Mid-Senior level Employment type
Contract Job function
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Nice-to-have skills

  • C
  • C++
  • Linux
  • Verilog
  • Windows
  • California, United States

Work experience

  • Embedded
  • Electronics Engineering

Languages

  • English
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