GPGPU Software Architect/ Principal EngineerXPENG • Santa Clara, California, United States
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GPGPU Software Architect/ Principal Engineer
XPENG
- Santa Clara, California, United States
- Santa Clara, California, United States
À propos
Software Technical Strategy: Develop and refine a comprehensive 3-year roadmap for a software stack compatible with CUDA, encompassing Runtime, Driver, Compiler, Profiler, Debugger, and AI acceleration libraries Define binding specifications that link our upcoming GPU ISA to CUDA APIs, ensuring forward compatibility with CUDA 12.x features Evaluate and integrate the latest technological advancements: CUDA Graph, Transformer Engine, virtual memory management, CUDA dynamic CUTLASS 3.x, TMA, Blackwell FP4, among others Define the task launch protocol, including Queue, Stream, Event, and Graph, as well as the memory model Design a dual-mode (JIT & offline) compiler supporting LTO, PGO, Auto-Tuning, and efficient PTX→ISA microcode caching Develop GPU virtualization schemes (MIG) that work across processes and containers
Performance & Observability
Build an observability platform: Nsys-compatible traces, real-time Metric-QPS dashboards, and an AI Advisor for identifying bottlenecks automatically Manage internal AI benchmarks as the single source of truth. Benchmark includes MLPerf Inference, Stable Diffusion XL, and 70B LLM
Cross-functional Collaboration
Co-design ISA compatible with CUDA Compute Capability 12.x with our hardware architecture team Collaborate with AI framework teams (PyTorch, TensorFlow, JAX, ONNX Runtime) to build fully reusable kernel libraries Partner with Cloud and Kubernetes teams to co-develop Device Plugins, GPU Operators, and RDMA Network Policies 10 years+ in systems software, with at least 5 years in designing CUDA Compute stacks Led end-to-end development of a GPU Runtime or AI acceleration library generation Comprehensive mastery of PTX/SASS, CUDA Driver API, and cuBLAS/cuDNN internals; experience with LLVM NVPTX backend Profound understanding of GPU micro-architecture, including SM architecture, Warp Scheduler, Shared-Memory conflicts, and Tensor Core pipelines Proficiency with PCIe/CXL/RDMA topologies, NUMA settings, and GPU Direct RDMA/Storage
Compensation The base salary range for this full-time position is $241,800 - $409,200 in addition to bonus, equity and benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Equity, Benefits & Equal Opportunity We are an Equal Opportunity Employer. It is our policy to provide equal employment opportunities to all qualified persons without regard to race, age, color, sex, sexual orientation, religion, national origin, disability, veteran status or marital status or any other prescribed category set forth in federal or state regulations. Location Santa Clara, CA Experience & Seniority
Seniority level: Director Employment type: Full-time Job function: Industries — Motor Vehicle Manufacturing
Benefits
Medical insurance Vision insurance 401(k)
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Compétences linguistiques
- English
Avis aux utilisateurs
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