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Senior Staff Engineer, GPU Design Verification (Formal Verification)
- San Jose, Arizona, United States
- San Jose, Arizona, United States
About
Samsung, a world leader in advanced semiconductor technology, is building a center of excellence for Intellectual Property applied to high‑performance computing devices for mobile, automotive, and other custom market segments. Role and Responsibilities
Shape block and subsystem level formal verification for Samsung’s next‑generation mobile GPU. Contribute to formal verification strategy and hands‑on verification of GPU designs, ensuring functional correctness, power gating mechanisms, and architectural intent. Define verification goals, properties, coverage objectives and sign‑off criteria for critical GPU features, including clock and power gating. Develop assertions, properties and formal models with architecture and RTL teams using industry‑standard formal tools and methodologies. Apply formal techniques to exhaustively verify corner cases, state‑space behaviors and safety properties beyond simulation‑based verification. Analyze formal failures, trace counterexamples and collaborate closely with design and architecture teams to resolve root causes and improve design robustness. Implement advanced formal verification techniques such as proof depth, bug hunting, complexity handling, bounded proof, failure triaging, coverage analysis and convergence analysis to achieve formal closure of GPU design features. Maintain documentation for formal verification test plans, convergence reports, complexity analysis reports and results using Confluence, JIRA and related tools. Mentor engineers and foster ownership, accountability and innovation in a fast‑paced global team. Skills and Qualifications
10+ years of experience with a Bachelor’s Degree; 8+ years with a Master’s; or 6+ years with a Ph.D. 8+ years of hands‑on GPU, CPU or advanced semiconductor design verification with a focus on formal verification. Strong understanding of computer architecture and graphics pipelines. Proficient programming and scripting skills in Python, Perl, C/C++ or equivalent. Proficient in SystemVerilog and SystemVerilog Assertions (SVA). Expertise in formal verification methodologies, including property verification, data‑path checking, model checking, register verification, connectivity checking and coverage analysis. Hands‑on experience with industry‑standard formal verification EDA tools and methodologies. Excellent debugging, analytical and problem‑solving skills; ability to identify bottlenecks and propose solutions. Strong communication and collaboration skills; ability to navigate ambiguity and influence in a global team environment. Nice to have: knowledge of memory subsystem or coherent interconnects. Proficiency in constrained random verification using IEEE 1800‑UVM. Experience developing new formal verification methodologies, flows or tooling. Exposure to low‑power design techniques and verification of power intent (e.g., UPF concepts). Demonstrated passion for innovation and advancing formal verification practices. Benefits
Base pay range: $198,200 – $297,200. Medical, dental, vision, life insurance and 401(k). On‑site lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program and wellness incentives. Eligible for MBO bonus compensation and potentially long‑term incentive plan and relocation. Exempt position, not eligible for overtime. Equal Employment Opportunity
Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.
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