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About
Implement advanced Ethernet protocols for next-generation Ethernet ASICs Write micro architecture specifications and define timing constraints for RTL blocks Collaborate with verification engineers to create test plans and resolve post-silicon ASIC issues
Required Qualifications
B.S. or M.S. degree in Computer or Electrical Engineering 3+ years of experience in digital design with proficiency in Verilog and System Verilog Experience in timing closure and familiarity with modern physical design methodologies Demonstrated ability in system-level debugging and root cause analysis
Languages
- English
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