Sr. Digital Design Engineer
Analog Group
- San Jose, Arizona, United States
- San Jose, Arizona, United States
About
Digital Design (RTL design): ASIC or FPGA from concept to implementation. Digital Verification: Development test plans, test benches and automated test cases. Responsible for synthesis, timing closure, and formal verification. Create scripting to support design and verification automation. Estimate and manage time/tasks completion to target schedule. Qualifications:
3-5 years’ experience in design plus verification of ASIC or FPGA. Strong knowledge of ASIC development process and digital design techniques. Proficient in standard DV languages (Verilog, SystemVerilog, UVM) and automated regression testcase development, and reporting/tracking coverage metrics. Experience with:
Programming, scripting and automation languages (C/C++, shell, Perl, TCL, Python, etc.). Digital signal processing and filter design.
Experience with the following desired:
Audio or video applications.
Embedded designs and/or firmware development. Knowledge of power management industry/applications. I2C, SPI, USB, PMBUS. Education:
Requires MSEE/Ph.D. or equivalent. Reference Number: MMMP113 Job Features
Job Category Digital,Digital Power,Firmware/Embedded,Power Management,Semiconductor
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Languages
- English
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