This job offer is no longer available
Senior Analog Layout Engineer - Timing-Critical Chips
jobtraffic
- Ireland
- Ireland
About
Interested in this role You can find all the relevant information in the description below.
The ideal candidate will have a minimum of 5 years of experience, ideally more than 8, in analog layout engineering.
Expertise in layout for critical timing, particularly for PLLs and DLLs, is essential.
Experience with Cadence tools is also required. xcfaprz
This role offers the opportunity to work in a dynamic environment with a focus on advanced technologies and layout practices.
#J-18808-Ljbffr
Languages
- English
Notice for Users
This job was posted by one of our partners. You can view the original job source here.